Stacked package including spacers and method of manufacturing the same

ABSTRACT

A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Continuation of U.S. application Ser. No.13/311,681, filed Dec. 6, 2011, which claims priority from Korean PatentApplication No. 2011-13128, filed on Feb. 15, 2011 in the KoreanIntellectual Property Office, the contents of both applications areherein incorporated by reference in their entirety.

BACKGROUND

1. Field

Article of manufacture and methods consistent with exemplary embodimentsrelate to a stacked package and a method of manufacturing the same and,more particularly, to a stacked package including sequentially stackedsemiconductor packages, and a method of manufacturing the stackedpackage.

2. Description of the Related Art

Generally, a plurality of semiconductor fabrication processes may beperformed on a semiconductor substrate to form a plurality ofsemiconductor chips. In order to mount the semiconductor chips on aprinted circuit board (PCB), a packaging process may be performed on thesemiconductor chips to form semiconductor packages. Further, in order toincrease storage capacity of the semiconductor package, a stackedpackage including sequentially stacked semiconductor packages may beused.

The stacked package may include several semiconductor packages andplugs, in which the semiconductor packages are stacked on one anotherand the plugs provide electrical connections between the packages.

In order to attach the plugs to the packages, heat may be applied to theplugs. While applying the heat to the plugs, the plugs may becomeliquefied and compressed such that an electrical short may be generatedbetween adjacent plugs.

SUMMARY

One or more exemplary embodiments provide a stacked package capable ofpreventing an electrical short between plugs.

One or more exemplary embodiments also provide a method of manufacturingthe above-mentioned stacked package.

According to an aspect of an exemplary embodiment, there is provided astacked package. The stacked package may include a first semiconductorpackage, a second semiconductor package, a plurality of plugs and aplurality of spacers. The second semiconductor package may be stacked onthe first semiconductor package. The plugs may electrically connect thefirst semiconductor to the second semiconductor package. The spacers maybe interposed between the first semiconductor package and the secondsemiconductor package to form a gap between the first semiconductorpackage and the second semiconductor package, thereby preventing anelectrical short between the plugs.

The spacers may be positioned at corners between the first semiconductorpackage and the second semiconductor package.

The spacers may be configured to individually surround each of theplugs.

The spacers may be configured to have a substantially same thickness.

The spacers may have a rounded upper configured to make point contactwith the second semiconductor package.

The spacer may have a first surface making contact with the secondsemiconductor package, and a second surface making contact with thefirst semiconductor package. The first surface may have an area smallerthan that of the second surface.

The spacers may have a gradually decreasing cross-sectional area in adirection from the first surface toward the second surface.

The spacer may be provided on the first semiconductor package.

The first semiconductor package may include a first package substrate, afirst semiconductor chip arranged on a surface of the first packagesubstrate and electrically connected with the first package substrate,and a first molding member formed on the surface of the first packagesubstrate. The first molding member may comprise spacers and plug holesconfigured to receive the plugs.

The first semiconductor package may further include conductive bumpsinterposed between the first package substrate and the firstsemiconductor chip to electrically connect the first package substratewith the first semiconductor chip.

The spacers may be provided to the second semiconductor package.

The second semiconductor package may include a second package substratestacked on the first semiconductor package, a second semiconductor chiparranged on a surface facing away from the first semiconductor packagewhen the second semiconductor package is stacked on the firstsemiconductor package and electrically connected with the second packagesubstrate, and a second molding member formed on the surface of thefirst package substrate. The second package substrate may beelectrically connected to the plugs. The second package substrate mayhave the spacers.

According to an aspect of another exemplary embodiment, there isprovided a method of manufacturing a stacked package. The methodcomprises preparing a first package substrate; arranging plugs on thefirst package substrate; forming spacers on the first package substrate;and stacking a second semiconductor package on the first packagesubstrate, the second semiconductor package electrically connected withthe first package substrate via the plugs, and the spacers interposedbetween the first package substrate and the second semiconductor packageto form a gap between the first package substrate and the secondsemiconductor package.

The preparing the first package substrate may comprise arranging a firstsemiconductor chip on a surface of the first package substrate.

The forming the spacers may comprise forming a first molding memberhaving the spacers on the surface of the first package substrate.

The method may further comprise, after forming the first molding member,forming plug holes in the first molding member.

The plug holes may be formed by partially removing a surface of thefirst molding member to expose the plugs using a drill process or anetching process.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or other aspects will be more clearly understood from thefollowing detailed description of exemplary embodiments taken inconjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view illustrating a stacked package inaccordance with an exemplary embodiment;

FIG. 2 is an enlarged cross-sectional view of a portion “II” in FIG. 1;

FIG. 3 is a plan view illustrating a first semiconductor package of thestacked package in FIG. 1;

FIGS. 4 to 10 are cross-sectional views illustrating a method ofmanufacturing the stacked package in FIG. 1;

FIG. 11 is a plan view illustrating a first semiconductor package of astacked package in accordance with another exemplary embodiment;

FIG. 12 is a plan view illustrating a first semiconductor package of astacked package in accordance with another exemplary embodiment;

FIG. 13 is a plan view illustrating a first semiconductor package of astacked package in accordance with another exemplary embodiment;

FIG. 14 is a plan view illustrating a stacked package in accordance withanother exemplary embodiment; and

FIGS. 15 to 21 are cross-sectional views illustrating a method ofmanufacturing the stacked package in FIG. 14.

DETAILED DESCRIPTION

Various exemplary embodiments will be described more fully hereinafterwith reference to the accompanying drawings. The present inventiveconcept may, however, be embodied in many different forms and should notbe construed as limited to the exemplary embodiments set forth herein.Rather, these exemplary embodiments are provided so that this disclosurewill be thorough and complete, and will fully convey the scope of thepresent inventive concept to those skilled in the art. In the drawings,the sizes and relative sizes of layers and regions may be exaggeratedfor clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexemplary embodiments only and is not intended to be limiting of thepresent invention. As used herein, the singular forms “a,” “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise. It will be further understood thatthe terms “comprises” and/or “comprising,” when used in thisspecification, specify the presence of stated features, integers, steps,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, elements, components, and/or groups thereof.

Exemplary embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized exemplary embodiments (and intermediate structures). As such,variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, exemplary embodiments should not be construed as limitedto the particular shapes of regions illustrated herein but are toinclude deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe present inventive concept.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, exemplary embodiments will be explained in detail withreference to the accompanying drawings.

FIG. 1 is a cross-sectional view illustrating a stacked package inaccordance with some exemplary embodiments, FIG. 2 is an enlargedcross-sectional view of a portion “II” in FIG. 1, and FIG. 3 is a planview illustrating a first semiconductor package of the stacked packagein FIG. 1.

Referring to FIGS. 1 to 3, a stacked package 300 of this exemplaryembodiment may include a first semiconductor package 100, plugs 180 anda second semiconductor package 200.

The first semiconductor package 100 may include a first packagesubstrate 110, a first semiconductor chip 120, conductive bumps 130, afirst molding member 140 and external terminals 150.

In some exemplary embodiments, the first package substrate 110 mayinclude an insulating substrate (not shown) and a circuit pattern (notshown). The circuit pattern may be built in the insulating substrate.The circuit pattern may have an upper end exposed through an uppersurface of the insulating substrate, and a lower end exposed through alower surface of the insulating substrate.

The first semiconductor chip 120 may be arranged on an upper centralsurface of the first package substrate 110. In some exemplaryembodiments, the first semiconductor chip 120 may have pads (not shown).The pads may be arranged on a lower surface of the first semiconductorchip 120. Thus, the pads may be oriented toward the first packagesubstrate 110. The first semiconductor chip 120 may include a logicchip.

The conductive bumps 130 may be interposed between the firstsemiconductor chip 120 and the first package substrate 110 toelectrically connect the pads of the first semiconductor chip 120 withthe circuit pattern of the first package substrate 110. In someexemplary embodiments, the conductive bumps 130 may include solderbumps.

The first molding member 140 may be formed on the upper surface of thefirst package substrate 110 to surround side surfaces of the firstsemiconductor chip 120. Thus, the first semiconductor chip 120 may havean exposed upper surface. Alternatively, the first molding member 140may be configured to cover the upper surface of the first semiconductorchip 120. The first molding member 140 may have plug holes 142 andspacers 144. In some exemplary embodiments, the first molding member 140may include an epoxy molding compound (EMC).

In some exemplary embodiments, the plug holes 142 may be verticallyformed through an edge portion of the first molding member 140. Theplugs 180 may be received in the plug holes 142. Thus, upper ends of theplugs 180 in the plug holes 142 may be exposed. In contrast, lower endsof the plugs 180 in the plug holes 142 may contact with the uppersurface of the first package substrate 110. The lower ends of the plugs180 in the plug holes 142 may be electrically connected to the circuitpattern of the first package substrate 110.

The spacers 144 may be formed on an upper surface of the first moldingmember 140. In some exemplary embodiments, the spacers 144 may be a partof the first molding member 140 protruded from the upper surface of thefirst molding member 140. Thus, the spacers 144 may be formed togetherwith formation of the first molding member 140. Alternatively, thespacers 144 may be formed by a separate process different from a processfor forming the first molding member 140.

In some exemplary embodiments, the spacers 144 may have a function as toform a gap between the first semiconductor package 100 and the secondsemiconductor package 200. In such as case, when the secondsemiconductor package 200 is attached to the first semiconductor package100, the second semiconductor package 200 may make contact with thespacers 144, so that the second semiconductor package 200 does notcompress the plugs 180 in the plug holes 142. As a result, during areflow process for attaching the plug 180 to the second semiconductorpackage 200, the spacers 144 may prevent an electrical short betweenadjacent liquefied plugs 180.

The liquefied plugs 180 may flow between the first molding member 140and the second semiconductor package 200 by a capillary phenomenon. Thecapillary phenomenon tends to increase in proportion to an interfacearea between the first molding member 140 and the second semiconductorpackage 200. In some cases, it is advantageous to prevent the capillaryphenomenon. Accordingly, in some exemplary embodiments, each of thespacers 144 may include a lower surface having a lower area, and anupper surface having an upper area smaller than the lower area. In someexemplary embodiments, each of the spacers 144 may have a graduallydecreased area in an upward direction.

In some cases, when the second semiconductor package 200 that makescontact with the spacers 144 leans, the plugs 180 may be partiallydisconnected with the second semiconductor package 200. In some cases,it is advantageous to prevent the disconnection between plugs 180 andthe second semiconductor package 200. Accordingly, in some exemplaryembodiments, the spacers 144 may have substantially the same thickness.

In some exemplary embodiments, four spacers 144 may be positioned atfour corners of the first molding member 140. Thus, the spacers 144having a uniform thickness may form a uniform gap between the firstsemiconductor package 100 and the second semiconductor package 200.

The external terminals 150 may be mounted on the lower surface of thefirst package substrate 110. The external terminals 150 may electricallymake contact with the circuit pattern exposed through the lower surfaceof the first package substrate 110. Thus, the external terminals 150 maybe electrically connected with the plugs 180. In some exemplaryembodiments, the external terminals 150 may include solder balls.

The second semiconductor package 200 may include a second packagesubstrate 210, a second semiconductor chip 220, conductive wires 230 anda second molding member 240.

In some exemplary embodiments, the second package substrate 210 may bearranged on the upper surface of the first molding member 140. Thus, alower surface of the second package substrate 210 may make contact withthe spacers 144. However, in some cases, the lower surface of the secondpackage substrate 210 may not make contact with the plugs 180. In someexemplary embodiments, the second package substrate 210 may include aninsulating substrate and a circuit pattern built in the insulatingsubstrate. The circuit pattern may be exposed through an upper surfaceand a lower surface of the insulating substrate.

The second semiconductor chip 220 may be arranged on an upper centralsurface of the second package substrate 210. The second semiconductorchip 220 may have pads (not shown). The pads may be arranged on an upperedge surface of the second semiconductor chip 220. In some exemplaryembodiments, the second semiconductor chip 220 may include a memorychip.

The conductive wires 230 may be electrically connected between the padsof the second semiconductor chip 220 and the circuit pattern of thesecond package substrate 210. In some exemplary embodiments, theconductive wires 230 may include a metal wire such as a gold wire.

The second molding member 240 may be formed on the upper surface of thesecond package substrate 210 to cover the second semiconductor chip 220and the conductive wires 230. The second molding member 240 may includean EMC.

According to this exemplary embodiment, the spacers located at the fourcorners of the first molding member may prevent a contact between thesecond semiconductor package and the plugs. Thus, an electrical shortbetween the adjacent liquefied plugs may be prevented.

FIGS. 4 to 10 are cross-sectional views illustrating a method ofmanufacturing the stacked package in FIG. 1.

Referring to FIG. 4, the conductive bumps 130 may be attached to theupper surface of the first package substrate 110. The firstsemiconductor chip 120 may be attached to the conductive bumps 130. Areflow process may be performed on the conductive bumps 130 toelectrically connect the first semiconductor chip 120 with the firstpackage substrate 110 via the conductive bumps 130.

Referring to FIG. 5, the plugs 180 may be attached to the upper surfaceof the first package substrate 110. The external terminals 150 may bemounted on the lower surface of the first package substrate 110.

Referring to FIG. 6, the first molding member 140 may be formed on theupper surface of the first package substrate 110 to cover the plugs 180and the first semiconductor chip 120. In some exemplary embodiments, thefirst molding member 140 may be configured to surround the side surfacesof the first semiconductor chip 120. Thus, the upper surface of thefirst semiconductor chip 120 may be exposed.

In some exemplary embodiments, the first molding member 140 may have thefour spacers 144, as shown in FIG. 6. The spacers 144 may be formed onthe corners of the upper surface of the first molding member 140. Thespacers 144 may be positioned so as not to overlap with the plugs 180.

Referring to FIG. 7, the upper surface of the first molding member 140may be partially removed to form the plug holes 142 configured to exposethe plugs 180, thereby completing the first semiconductor package 100.In some exemplary embodiments, the upper surface of the first moldingmember 140 may be removed by using a drill process, an etch process,etc.

Referring to FIG. 8, the second semiconductor chip 220 may be attachedto the upper central surface of the second package substrate 210.

Referring to FIG. 9, the conductive wires 230 may be connected betweenthe pads of the second semiconductor chip 220 and the circuit pattern ofthe second package substrate 210.

Referring to FIG. 10, the second molding member 240 may be formed on theupper surface of the second package substrate 210 to cover the secondsemiconductor chip 220 and the conductive wires 230, thereby completingthe second semiconductor package 200.

The second semiconductor package 200 may be arranged on the firstsemiconductor package 100. The lower surface of the second packagesubstrate 210 may make contact with the spacers 144, such that the lowersurface of the second package substrate 210 does not make contact withthe plugs 180.

The reflow process may be performed on the plugs 180 and the externalterminals 150. The external terminals 150 may be firmly fixed to thelower surface of the first package substrate 110.

In some cases, when the solid plugs 180 are converted into liquefiedplugs by the heat generated during the reflow process, the liquefiedplugs 180 may be connected with each other. However, according to theexemplary embodiment, because the spacers 144 may form the gap betweenthe first molding member 140 and the second package substrate 210, theliquefied plug 180 may be prevented from flowing into the adjacentliquefied plug 180, so that an electrical short between the liquefiedplugs 180 may be prevented. Further, because the upper surface of thespacers 144 may have an upper area smaller than a lower area of thelower surface of the spacers 144, the capillary phenomenon, by which theliquefied plug 180 flows into the adjacent liquefied plug 180 through aninterface between the spacer 144 and the second package substrate 210,may be suppressed. As a result, the electrical short between theadjacent plugs 180 may be prevented.

When the liquefied plugs 180 may be cooled, the solid plugs 180 may befirmly secured to the first package substrate 110 and the second packagesubstrate 210. Thus, the stacked package 300 in FIG. 1 including thefirst semiconductor package 100 and the second semiconductor package 200connected with each other via the plugs 180 may be completed.

FIG. 11 is a plan view illustrating a first semiconductor package of astacked package in accordance with another exemplary embodiment.

The stacked package 300 a of this exemplary embodiment may includeelements substantially the same as those of the stacked package 300 inFIG. 1 except for the spacers. Thus, the same reference numerals mayrefer to the same elements, and any further illustrations with respectto the same elements are omitted herein for brevity.

Referring to FIG. 11, the stacked package 300 a in accordance with thisexemplary embodiment may include eight spacers 144 a at the corners ofthe first molding member 140, and two spacers 144 a at a central surfaceof the first molding member 140. A pair (i.e., two) of the spacers 144 amay be positioned at each of the corners of the first molding member140. Thus, the spacers 144 a may more firmly support the secondsemiconductor package 200 compared to the spacers 144 in FIG. 1.

FIG. 12 is a plan view illustrating a first semiconductor package of astacked package in accordance with another exemplary embodiment.

The stacked package 300 b of this exemplary embodiment may includeelements substantially the same as those of the stacked package 300 inFIG. 1 except for the spacers. Thus, the same reference numerals mayrefer to the same elements, and any further illustrations with respectto the same elements are omitted herein for brevity.

Referring to FIG. 12, the stacked package 300 b in accordance with thisexemplary embodiment may include stripe-shaped spacers 144 b extendingon an upper edge surface of the first molding member 140 in two rowsalong lengthwise and breadthwise directions. The stripe-shaped spacers144 b may intersect with each other at the corners of the first moldingmember 140. Thus, the stripe-shaped spacers 144 b may more firmlysupport the second semiconductor package 200 compared to the spacers 144in FIG. 1 and the spacers 144 a in FIG. 11.

FIG. 13 is a plan view illustrating a first semiconductor package of astacked package in accordance with another exemplary embodiment.

The stacked package 300 c of this exemplary embodiment may includeelements substantially the same as those of the stacked package 300 inFIG. 1 except for the spacers. Thus, the same reference numerals mayrefer to the same elements, and any further illustrations with respectto the same elements may be omitted herein for brevity.

Referring to FIG. 13, the stacked package 300 c in accordance with thisexemplary embodiment may include a spacer 144 c configured toindividually surround the plugs 180 exposed through the upper surface ofthe first molding member 140. Thus, the spacer 144 c may more firmlysupport the second semiconductor package 200 compared to the spacers 144in FIG. 1, the spacers 144 a in FIG. 11 and the spacers 144 b in FIG.12. Further, because the spacer 144 c may individually surround each ofthe plugs 180, if heat is applied and the plugs 180 liquefy, the flow ofthe plug 180 toward the adjacent plug 180 may be suppressed.

FIG. 14 is a plan view illustrating a stacked package in accordance withanother exemplary embodiment.

The stacked package 300 d of this exemplary embodiment may includeelements substantially the same as those of the stacked package 300 inFIG. 1 except for the spacers. Thus, the same reference numerals mayrefer to the same elements, and any further illustrations with respectto the same elements are omitted herein for brevity.

Referring to FIG. 14, the stacked package 300 d in accordance with thisexemplary embodiment may include spacers 210 d formed on the lowersurface of the second package substrate 210. The spacers 210 d may beformed together with the formation of the second package substrate 210.Alternatively, the spacers 210 d may be formed by a separate processdifferent from a process for forming the second package substrate 210.

The spacers 210 d of the second package substrate 210 may make contactwith the upper surface of the first molding member 140 to prevent acontact between the second package substrate 210 and the plugs 180.

In some exemplary embodiments, the spacers 210 d may have functionssubstantially the same as those of the spacers 144 in FIG. 1. Thus, anyfurther illustrations with respect to the spacers 210 d are omittedherein for brevity. Further, the spacers 210 d may have a shapesubstantially the same as that of the spacers 144 in FIG. 3, the spacers144 a in FIG. 11, the spacers 144 b in FIG. 12 or the spacers 144 c inFIG. 13. One of ordinary skill in the art will also appreciate that oneor more spacers may be formed both on the second package substrate 210and the first package substrate 110. In such a case, it is advantageousif the one or more spacers on the second packages substrate 210 areformed in locations different than the one or more spacers on the firstpackage substrate 110 so as not to increase the space between thepackages so much that the packages cannot be electrically connectedtogether.

FIGS. 15 to 21 are cross-sectional views illustrating a method ofmanufacturing the stacked package in FIG. 14.

Referring to FIG. 15, the conductive bumps 130 may be attached to theupper surface of the first package substrate 110. The firstsemiconductor chip 120 may be attached to the conductive bumps 130. Thereflow process may be performed on the conductive bumps 130 toelectrically connect the first semiconductor chip 120 with the firstpackage substrate 110 via the conductive bumps 130.

Referring to FIG. 16, the plugs 180 may be attached to the upper surfaceof the first package substrate 110. The external terminals 150 may bemounted on the lower surface of the first package substrate 110.

Referring to FIG. 17, the first molding member 140 may be formed on theupper surface of the first package substrate 110 to cover the plugs 180and the first semiconductor chip 120. In some exemplary embodiments, thefirst molding member 140 may surround the side surfaces of the firstsemiconductor chip 120. Thus, the upper surface of the firstsemiconductor chip 120 may be exposed.

Referring to FIG. 18, the upper surface of the first molding member 140may be partially removed to form the plug holes 142 configured to exposethe plugs 180, thereby completing the first semiconductor package 100.In some exemplary embodiments, the upper surface of the first moldingmember 140 may be removed by a drill process, an etch process, etc.

Referring to FIG. 19, the second semiconductor chip 220 may be attachedto the upper central surface of the second package substrate 210. Insome exemplary embodiments, the spacers 210 d may be formed on the lowersurface of the second package substrate 210.

Referring to FIG. 20, the conductive wires 230 may be connected betweenthe pads of the second semiconductor chip 220 and the circuit pattern ofthe second package substrate 210.

Referring to FIG. 21, the second molding member 240 may be formed on theupper surface of the second package substrate 210 to cover the secondsemiconductor chip 220 and the conductive wires 230, thereby completingthe second semiconductor package 200.

The second semiconductor package 200 may be arranged on the firstsemiconductor package 100. The upper surface of the first molding member140 may make contact with the spacers 210 d. In contrast, the lowersurface of the second package substrate 210 may be positioned so as notto make contact with the plugs 180.

The reflow process may be performed on the plugs 180 and the externalterminals 150. The external terminals 150 may be firmly fixed to thelower surface of the first package substrate 110.

When the liquefied plugs 180 are cooled, the solid plugs 180 may befirmly secured to the first package substrate 110 and the second packagesubstrate 210. Thus, the stacked package 300 d in FIG. 14 including thefirst semiconductor package 100 and the second semiconductor package 200connected with each other via the plugs 180 may be completed.

According to the exemplary embodiments, the spacer may prevent thecontact between the plugs and the second semiconductor package. Thus, anelectrical short between the plugs may be prevented.

The foregoing is illustrative of exemplary embodiments and is not to beconstrued as limiting thereof. Although a few exemplary embodiments havebeen described, those skilled in the art will readily appreciate thatmany modifications are possible in the exemplary embodiments withoutmaterially departing from the novel teachings and advantages of thepresent inventive concept. Accordingly, all such modifications areintended to be included within the scope of the present inventiveconcept as defined in the claims. In the claims, means-plus-functionclauses are intended to cover the structures described herein asperforming the recited function and not only structural equivalents butalso equivalent structures. Therefore, it is to be understood that theforegoing is illustrative of various exemplary embodiments and is not tobe construed as limited to the specific exemplary embodiments disclosed,and that modifications to the disclosed exemplary embodiments, as wellas other exemplary embodiments, are intended to be included within thescope of the appended claims.

What is claimed is:
 1. A stacked package comprising: a firstsemiconductor package; a second semiconductor package stacked on thefirst semiconductor package; a plurality of plugs configured toelectrically connect the first semiconductor package with the secondsemiconductor package; and a plurality of spacers configured to preventan electrical short between the plugs, the spacers interposed betweenthe first semiconductor package and the second semiconductor package andforming a gap between the first semiconductor package and the secondsemiconductor package.
 2. The stacked package of claim 1, wherein thespacers are arranged at corners between the first semiconductor packageand the second semiconductor package.
 3. The stacked package of claim 1,wherein the spacers are configured to individually surround the plugs.4. The stacked package of claim 1, wherein the spacers have asubstantially same thickness.
 5. The stacked package of claim 1, whereineach of the spacers has a rounded surface configured to contact with thesecond semiconductor package.
 6. The stacked package of claim 1, whereineach of the spacers have a first surface that contacts the firstsemiconductor package, and a second surface that contacts the secondsemiconductor package and has an area smaller than that of the firstsurface.
 7. The stacked package of claim 6, wherein each of the spacershas cross-sectional area that gradually decreases in a direction fromthe first surface toward to the second surface.
 8. The stacked packageof claim 1, wherein the spacers are disposed on the first semiconductorpackage.
 9. The stacked package of claim 8, wherein the firstsemiconductor package comprises: a first package substrate; a firstsemiconductor chip disposed on a surface of the first package substratethat faces the second semiconductor package, the first semiconductorchip electrically connected with the first package substrate; and afirst molding member disposed on the surface of the first packagesubstrate, the first molding member comprising the spacers and plugholes configured to receive the plugs.
 10. The stacked package of claim9, wherein the first semiconductor package further comprises conductivebumps interposed between the first package substrate and the firstsemiconductor chip to electrically connect the first package substratewith the first semiconductor chip.
 11. The stacked package of claim 1,wherein the spacers are provided on the second semiconductor package.12. The stacked package of claim 11, wherein the second semiconductorpackage comprises: a second package substrate disposed on the firstsemiconductor package and electrically connected to the plugs, thesecond package substrate comprising the spacers; a second semiconductorchip disposed on a surface of the second package substrate facing awayfrom the first semiconductor package when the second semiconductorpackage is disposed on the first semiconductor package, the secondsemiconductor chip electrically connected with the second packagesubstrate; and a second molding member disposed on the surface of thesecond package substrate.
 13. The stacked package of claim 1, whereinthe spacers are provided on both the first semiconductor package and thesecond semiconductor package.
 14. A method of manufacturing a stackedpackage, the method comprising: preparing a first package substrate;arranging plugs on the first package substrate; forming spacers on thefirst package substrate; and stacking a second semiconductor package onthe first package substrate, the second semiconductor packageelectrically connected with the first package substrate via the plugs,and the spacers interposed between the first package substrate and thesecond semiconductor package to form a gap between the first packagesubstrate and the second semiconductor package.
 15. The method of claim14, wherein preparing the first package substrate comprises: arranging afirst semiconductor chip on a surface of the first package substrate.16. The method of claim 15, wherein forming the spacers comprises:forming a first molding member having the spacers on the surface of thefirst package substrate.
 17. The method of claim 16, further comprisingafter forming the first molding member: forming plug holes in the firstmolding member.
 18. The method of claim 17, wherein the plug holes areformed by partially removing a surface of the first molding member toexpose the plugs using a drill process or an etching process.
 19. Astacked package comprising: a first semiconductor package; a secondsemiconductor package stacked on the first semiconductor package; aplurality of spacers formed between the first semiconductor package andthe second semiconductor package, each of the spacers having asubstantially same height, and a plurality of plugs that electricallyconnect the first semiconductor package and the second semiconductorpackage, wherein the spacers are configured to permit electricalconnection between the first semiconductor package and the secondsemiconductor package by the plugs and to prevent adjacent plugs fromelectrically connecting to each other by capillary action, duringheating of the stacked package.